The present invention relates generally to semiconductor devices, and more particularly to the formation of long channel transistors using a vertical-channel field effect transistor (FET) fabrication process.
A field effect transistor (FET) typically has a source region, a channel region, and a drain region, where current flows from the source region to the drain region, and a gate that controls the flow of current through the channel to operate the transistor. A vertical field-effect (FET) transistor has a channel perpendicular to the substrate surface, as opposed to being situated along the plane of the surface of the substrate.
The fabrication of semiconductor devices involves forming electronic components in and on semiconductor substrates, such as silicon wafers. These electronic components may include one or more conductive layers, one or more insulation layers, and doped regions formed by implanting various dopants into portions of a semiconductor substrate to achieve specific electrical properties. Semiconductor devices include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the semiconductor devices to form integrated circuits.
To electrically isolate semiconductor devices from each other, various isolation techniques, such as trench isolation structures, have been used. Viewing the vertical direction as into the depth, or thickness, of a given substrate and the horizontal direction as being parallel to a top surface of the substrate, a trench isolation structure is vertically oriented to provide insulating separation between semiconductor devices at different horizontal locations. Traditionally, a semiconductor surface is etched to form separate device regions, and resulting trenches in between the separate device regions are filled with dielectric material to form the trench isolation structures.